Own all aspects of the physical design flow, including floorplanning, placement, clock tree synthesis, routing, and Design for Manufacturability (DFM)
Utilize industry-leading EDA tools from Cadence and Synopsys for place and route, physical verification, static timing analysis (STA), power analysis, power integrity analysis and other signoff analysis.
Design Methodology in-depth expertise, specifically on Placement and Routing in Finfet and multi-patterning based process technologies using Cadence Innovus or Synopsys Fusion Compiler.
Collaborate closely with designers, verification engineers, and other stakeholders to achieve timing closure, ir drop and em closure, address signal integrity issues and resolve layout violations
Continuously improve physical design methodologies and scripts to enhance efficiency and flow consistency
Stay at the forefront of advancements in physical design technology and new process nodes

Requirements

Master's degree in Electrical Engineering or Computer Engineering (or a related field)
Minimum of 5 years of experience in physical design of integrated circuits
Proven expertise in the physical design flow, including placement, routing, clock tree synthesis, and physical verification
In-depth understanding of digital circuit design principles and concepts
Strong proficiency with industry-standard EDA tools (e.g., Cadence, Synopsys)
Excellent analytical and problem-solving skills
Ability to work effectively in a team environment and communicate complex technical concepts clearly
Experience with scripting languages (e.g., TCL, Python) a plus

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